Implement high-precision timing control logic to accurately generate the internal timing signals required for various operations (such as tR, tPROG, tBERS, etc.);
Deeply involved in the physical layer and link layer logic implementation of ONFI (Open NAND Flash Interface) or Toggle Mode interface protocols, supporting DDR, NV-DDR, NV-LPDDR, and other modes;
Collaborate with the analog/mixed-signal team to define array access timing, voltage switching windows, and read/write path control interfaces;
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