Yield & Failure Analysis– Experience analysing wafer sort, assembly, and final test data to identify yield issues, correlate failures across manufacturing stages, and determine root causes.
Develop and execute scripts using UNIX/Linux environments and scripting languages such as TCL and Bash to automate design tasks and improve workflow efficiency
Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes; 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage; 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred; 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++; 5. Familiar with 3D IC design; relevant experience is a plus; 6. Prior experience with STA signoff in tape-out projects is preferred.
Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones