Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).
Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
More than 2~7 years of hands-on experience in custom IC layout for Standard Cell, Memory Compiler or IO/ESD libraries using advanced finFET/GAA process nodes; candidates with Analog/RF experiences are welcomed to apply.
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Qualification 1. Candidate must possess at least Higher Secondary/STPM/"A" Level/Pre-U, Diploma/Advanced/Higher/Graduate Diploma in any field. 2. Required language(s): Bahasa Malaysia, English. 3. At least 1 Year(s) of working experience in the related field is required for this position. 4. Required Skill(s): Communication, Leadership, Independent, Supervision, Problem Solving 5. Able to work shift (day & night) rotation.
Responsibility 1. Assist supervisor in line arrangement.2. Assist supervisor for line quality issue of root cause study and implementation of improvement actions.3. Ensure daily target output is meet.4. Ensure all output send to warehouse.
Function 1. Verified daily output.2. Ensure operator follow SOI.3. Managing own work area and responsible for the facilities and equipment assigned with care.4. Work in accordance with safety and environmental standards.
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