Test Hardware Integration: Collaborate with PCB and probe card designers to optimize test hardware for power and signal integrity at high speed (PCIe Gen6, HBM4, Maxphy, 400G+ SerDes). Actively debug hardware-software interface issues on the loadboard and probe card levels.
Develop an action plan for regional coverage so that all existing and potential customers are met at regular intervals and that adequate cold calls, suspect calls and prospect calls are planned for the period to develop the potential pipeline.
Track developments and propose recommendations/follow-ups from APAC, Global ACI Executive Committees, General Assemblies, and related meetings, and ensure timely follow-through.