Debug complex HW/SW issues using DOE and root-cause analysis. Partner with design, layout, and firmware teams to enforce Design-for-Test (DFT) standards.
Quality Engineering Writing, reviewing and approving quality plans, inspection procedures, test automation, data management testing and testing protocols to ensure products consistently meet specifications.
Coach teams on reliability failure investigations, ensuring a deep understanding of failure mechanisms and stress test behaviors in accordance with JEDEC and AEC-Q standards.
Facilitate and lead structured problem-solving activities using methodologies such as Six Sigma, 8D, and 5 Why Analysis to identify root causes and implement effective corrective and preventive actions.
Drive hands-on design evaluation, hardware validation, first article assessment, debug, documentation, and release-to-production activities for wafer test hardware