Hands-on experience in FPGA RTL design, testbench development, logic verification, timing closure and debugging.
Expert in one or more FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features.
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Develop automation flows for layout synthesis, parameter sweeps, geometry optimization, and rule-driven layout adaptation.
Implement layout‑to‑EM extraction flows enabling high‑accuracy simulation of parameterized geometries.
Contribute domain expertise in RFIC and RF module design, including linear and nonlinear circuits, matching networks, filters, oscillators, PAs, and mixers.
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