Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.
Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.3.Researches the physical design methodology of advanced process nodes, and improvise the automatic physical design platform.
TOP role for the complicated hierarchical chip (more than 20 million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout.