Collaboration: Work closely with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets
Full Design Flow: Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation
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Collaboration: Work closely with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets
Full Design Flow: Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation
...
Expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team.
Willing to work in Penang, Malaysia.
Minimum 7+ years of physical design experience in converging the block.
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