Perform design self-check based on the design review checklist provided and fix the design accordingly.
Perform design cleanup with PLA tools. (Depend on the accessibility of the PLA tools)
Full package design including all/partial interfaces assignment as well as power assignment according to schematic that provided. Might include the component placement and constraint setting as well as other package design related request.
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With the relevant technical competencies, lead and execute product realization from conceptual stages all the way thru manufacturing transition.
Able to support the development of technical proposals for customers, providing technical solutions to realize concepts and estimating associated labor and material costs required.
Recognized subject matter expert for one or more technical areas. See Technical Competencies section.
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With the relevant technical competencies, lead and execute product realization from conceptual stages all the way thru manufacturing transition.
Able to support the development of technical proposals for customers, providing technical solutions to realize concepts and estimating associated labor and material costs required.
Recognized subject matter expert for one or more technical areas. See Technical Competencies section.
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Silicon One is seeking a highly skilled and motivated Custom Layout Engineer to join our elite engineering team. We deliver comprehensive, end-to-end IC design solutions—spanning logic and circuit design through to full physical implementation and tape-out.
In this role, you will collaborate with industry veterans to ensure our high-performance designs meet world-class specifications across advanced process nodes.
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Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).
Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
More than 2~7 years of hands-on experience in custom IC layout for Standard Cell, Memory Compiler or IO/ESD libraries using advanced finFET/GAA process nodes; candidates with Analog/RF experiences are welcomed to apply.
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Expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team.
Willing to work in Penang, Malaysia.
Minimum 7+ years of physical design experience in converging the block.
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