UST Hiring! Full Time CAD Flow Engineer – Physical Design in Pulau Pinang - Ricebowl

We are seeking a highly motivated CAD Flow Engineer to develop, maintain, and enhance Physical Design implementation flows for advanced-node ASIC and SoC projects. The ideal candidate will have strong expertise in EDA tools, automation, methodology development, and flow optimization across RTL-to-GDSII implementation.

The role involves close collaboration with Physical Design, STA, DFT, RTL, and CAD teams to deliver robust, scalable, and efficient design methodologies that improve design productivity, QoR, and turnaround time.

Key Responsibilities

• Develop, maintain, and support Physical Design implementation flows across advanced process nodes.
• Customize and optimize flows using Synopsys Fusion Compiler, PrimeTime, ICC2, Formality, and related EDA tools.
• Design and maintain automation frameworks using TCL, Python, Perl, and Shell scripting.
• Create reusable infrastructure for synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff activities.
• Develop QoR tracking, regression, reporting, and design health monitoring solutions.
• Debug flow issues, tool crashes, runtime bottlenecks, and methodology-related challenges.
• Collaborate with implementation teams to improve timing, power, area, congestion, and turnaround time.
• Enable new tool releases and drive tool qualification across projects.
• Develop methodologies for MCMM timing analysis, ECO flows, and signoff convergence.
• Work closely with EDA vendors to investigate tool issues and evaluate new features.
• Support deployment of advanced-node implementation methodologies (5nm, 3nm, and beyond).
• Create and maintain user documentation, flow guidelines, and training materials.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline.
• 5-8 years of experience in VLSI CAD, Physical Design, Implementation Methodology, or Design Automation.
• Strong understanding of digital ASIC implementation flows from RTL to GDSII.
• Hands-on experience with:

Synopsys Fusion Compiler

Synopsys PrimeTime

ICC2

Formality

Design Compiler

• Strong scripting expertise in:

TCL (mandatory)

Python

Shell scripting

• Experience developing CAD infrastructure, regressions, automation utilities, and flow enhancements.
• Experience debugging timing, constraint, and methodology-related issues.
• Familiarity with Linux/Unix environments.