UST Hiring! Full Time Design Verification (Memory controller) in Pulau Pinang - Ricebowl

Key Responsibilities

• Develop and execute verification plans for Memory Controller IPs and subsystems.
• Build and maintain verification environments using SystemVerilog and UVM.
• Create testcases, assertions, scoreboards, and coverage models.
• Perform functional, protocol, and performance verification for DDR/LPDDR-based designs.
• Debug RTL and verification issues, analyze coverage, and drive closure.
• Work closely with Design, Architecture, and SoC teams throughout the product lifecycle.
• Mentor junior verification engineers and contribute to verification methodology improvements.

Requirements

• 6–8 years of experience in Design Verification within the semiconductor industry.
• Strong expertise in:
• SystemVerilog
• UVM
• Assertions (SVA)
• Functional Coverage
• Constrained Random Verification
• Hands-on experience with simulation/debug tools such as VCS, Xcelium, Questa, and Verdi.
• Strong understanding of AXI/AMBA protocols.
• Experience with Linux and scripting (Python/Shell/Perl/Tcl).

Preferred Skills

• Experience verifying Memory Controllers, DDR4/DDR5, LPDDR4/LPDDR5, or HBM.
• Experience with SoC-level verification and performance validation.
• Knowledge of memory architecture, scheduling, and arbitration concepts.
• Leadership or mentoring experience is a plus.