FOCALTRANS PTE. LTD. Hiring! Full Time Senior IC Logic Design - STA Engineer in Central Region (Singapore), Earn up to SGD 7,000 - Ricebowl

Job Responsibilities

1. Responsible for logic synthesis, LEC and ECO implementation, as well as quality control throughout the development process. Work closely with the front-end design team to establish timing constraints and ensure timely timing closure.
2. Responsible for full-chip STA execution and timing constraint quality control, working closely with the back-end design team to complete timing sign-off.

Job Requirements

1. Bachelor’s degree or above in Computer Engineering, Electrical/Electronic Engineering, Communications Engineering or a related discipline, with 8+ years of relevant industry experience.
2. Strong proficiency in SDC and hands-on experience with Design Compiler (DC), Formality and PrimeTime (PT), with solid Tcl scripting skil