Study and implement cutting-edge test strategies within your specialization
Scan track: own tile-level scan insertion, ATPG, and quality checks; perform scan DRC and non-scan analysis; generate and verify chip-level scan patterns; support Scan ATE bring-up and debug
SMS track: implement DFX SMS design on SRAM/ROM/latch arrays; develop and verify tile- and chip-level BIST and memory repair test cases; develop high-coverage, cost-effective production test patterns
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