Technical Implementation & Testing Management: Lead commissioning and technical implementation of MES solutions; manage acceptance test creation, execution, and approval; monitor technical implementations and support during ramp‑up.
Support & Collaboration : Collaborate closely with template and local teams, act as 2nd‑level support for template functions, and ensure effective engagement with MES partners and stakeholders.
For a more senior position level, manage all aspects of a large scale, complex, or significant engineering project, from start to finish, so that it is completed on time and within budget.
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Create, review, and coordinate Engineering Change Orders implementation with the CM partner and make process improvement recommendations.
Acts as a primary interface with the Teradyne NPI Ops team / Engineering team during the release of a new assemblies or revisions to assemblies already in use.
To work with the CM partner to drive operation improvement.
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Hands-on experience in FPGA RTL design, testbench development, logic verification, timing closure and debugging.
Expert in one or more FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features.
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Create, review, and coordinate Engineering Change Orders implementation with the CM partner and make process improvement recommendations.
Acts as a primary interface with the Teradyne NPI Ops team / Engineering team during the release of a new assemblies or revisions to assemblies already in use.
To work with the CM partner to drive operation improvement.
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Conduct and execute RODI and Water Treatment system improvements on reliability hardening, safety performance as well as cost optimization and reduction
Perform facility inspections and report on condition affecting operations
Derive plan and monitor RODI and Water Treatment predictive and preventive maintenance program supervise outsource service contracts
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Hands-on experience in FPGA RTL design, testbench development, logic verification, timing closure and debugging.
Expert in one or more FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features.
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