Experience in developing ATE SOC program from NPI stage to volume ramp stage and driving yield and test time reduction.
Solid understanding in semiconductor Structural (Scan and Memory BIST) and functional testing. Good understanding of eletronics engineering fundamental. Basic knowledge on CPU, DSP, GPU will be a plus.
Experience in one or more chiplet‑based or multi‑die products, including die‑to‑die (D2D) interfaces and associated test and yield challenges is a plus
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