11 Noc Engineer Jobs in Pulau Pinang - July 2026

Address issues such as missing timing arcs and missing clock information.
Generate timing reference models based on IP requirements
Compare timing models: Current proprietary format vs. Liberty format (.lib). ...

Posted

5 days ago

Design Verification (DV) Engineer Design Verification (DV) Engineer

Lattice Semiconductor

Undisclosed

全职

Bayan Lepas

Create and debug tests for DUT
Resolve bugs with remote designers
Good understanding of verification process from test plan to coverage completion ...

Posted

5 days ago

Silicon Integration Design Engineer - Timing Model Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor

Undisclosed

全职

Bayan Lepas

Address issues such as missing timing arcs and missing clock information.
Generate timing reference models based on IP requirements
Compare timing models: Current proprietary format vs. Liberty format (.lib). ...

Posted

15 days ago

Design Verification (DV) Engineer Design Verification (DV) Engineer

Lattice Semiconductor

Undisclosed

全职

Bayan Lepas

Create and debug tests for DUT
Resolve bugs with remote designers
Good understanding of verification process from test plan to coverage completion ...

Posted

15 days ago

Silicon Integration Design Engineer - Timing Model Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor

Undisclosed

全职

Bayan Lepas

Address issues such as missing timing arcs and missing clock information.
Generate timing reference models based on IP requirements
Compare timing models: Current proprietary format vs. Liberty format (.lib). ...

Posted

17 days ago

Staff IP Design Engineer (Functional Safety) Staff IP Design Engineer (Functional Safety)

Lattice Semiconductor

Undisclosed

全职

Bayan Lepas

Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.
Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus. ...

Posted

5 days ago

Principal AI Chip Design Engineer（MYS) Principal AI Chip Design Engineer（MYS)

Canaan Inc.

Undisclosed

全职

Malaysia

Translate architecture and microarchitecture specifications into clean, reusable, synthesizable RTL.
Lead SoC/IP integration, bus/interconnect integration, and top-level connectivity.
Work with verification teams on test plans, simulation debug, coverage improvement, and design quality. ...

Posted

9 days ago

Staff IP Design Engineer (Functional Safety) Staff IP Design Engineer (Functional Safety)

Lattice Semiconductor

Undisclosed

全职

Bayan Lepas

Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.
Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus. ...

Posted

15 days ago

Memory Validation Engineer Memory Validation Engineer

ThunderSoft

Undisclosed

全职

Malaysia

Executes electrical & functional test plans for processors using hardware & software validation tools, oscilloscopes, & logic analyzers.
Debug of electrical & functional issues of the memory sub-system of new processors
Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. ...

Posted

22 days ago