RTL design structure for effective and efficient synthesis implementation
Derive timing constraints from design spec, review and validate with respective designer/architect for signoff
Design-For-Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST all the way to advanced handling for performance/schedule/coverage trade-off
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· Develop and maintain detailed schedules, short-term look-ahead plans, resource requirements and progress tracking for assigned Mechanical and/or Electrical work scopes.
· Monitor actual progress against the approved project schedule and promptly report delays, constraints and recovery requirements to the Project Manager / Senior Project Engineer.
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