Documentation & Transition: Create and maintain technical documentation (schematics, specifications, BOMs). Support design transition to manufacturing and ensure successful product releases
Collaboration: Work closely with multi-disciplinary teams including software, mechanical, firmware, and test engineers to review and improve hardware designs
Language Support: Act as the primary technical liaison for projects involving Mandarin-speaking stakeholders and partners
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Collaborating effectively with cross-functional teams including PCB layout, mechanical, signal integrity, and manufacturing teams to conduct thorough design reviews, ensuring alignment with technical specifications and overall system requirements.
Developing and executing comprehensive hardware validation plans at system level.
Analyzing test results, troubleshoot issues, and drive root cause resolution.
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Identify and derive special handling from design spec, such as NDR, source-sync and latency/skew control DRC/LVS and RV debug and convergence, including analysis for waiver request
Low power design; vector-driven layout optimization and leakage/dynamic power control techniques
Provide technical guidance and review for team members in solving complex challenges, with high problem solving skill and critical thinking capability
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Collaborate with cross-functional teams (firmware, software, mechanical, validation, manufacturing) to ensure successful product integration and delivery.
Work closely with ODMs, suppliers, and external partners to manage hardware design and manufacturing processes.
Define and execute hardware validation strategies, including bring-up, debugging, and system-level testing.
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The Chief Digital Hardware Engineer is the technical leader for digital hardware engineering, providing both strategic direction and hands‑on expertise across board‑level digital design, FPGA/RTL development, and platform architecture. This highly visible role influences product execution, design quality, and long‑term capability building across the organization. You will shape scalable, high‑performance, and reliable digital architectures aligned with our Test & Measurement technology roadmap, while partnering closely with engineering, product, and executive stakeholders.
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Identify and derive special handling from design spec, such as NDR, source-sync and latency/skew control DRC/LVS and RV debug and convergence, including analysis for waiver request
Low power design; vector-driven layout optimization and leakage/dynamic power control techniques
Provide technical guidance and review for team members in solving complex challenges, with high problem solving skill and critical thinking capability
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With the relevant technical competencies, lead and execute product realization from conceptual stages all the way thru manufacturing transition.
Able to support the development of technical proposals for customers, providing technical solutions to realize concepts and estimating associated labor and material costs required.
Recognized subject matter expert for one or more technical areas. See Technical Competencies section.
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Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.
Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus.
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Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.
Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus.
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Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.
Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus.
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