- Singapore
AUREXIS TECH PTE. LTD. Hiring! Full Time Sr - DFT Engineer ( IP - ASIC - SoC) in , Earn up to SGD 7,800 - Ricebowl
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Job Description
Responsibilities
Main Responsibilities
Work closely with design teams and make sure DFT structures are correctly implemented
Responsible for verifying DFT schemes on IPs in ASIC and FPGA products
Responsible for block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes
Responsible for memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG
Responsible to develop firmware-driven cost-effective test methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench and ATE
Assist test pattern failure debug and diagnosis on FPGA-based test environment and ATE machine through product lifecycle
Main Requirements
Degree in Electrical/ Electronics/ Computer Engineering or equivalent with min 1 year DFT experience
Experience on pre-silicon DFT design specification and scan insertion
Engineering experience on DFT design verification (ATPG/MBIST/simulation)
Tessent Streaming Scan Network (SSN) hand-on experience is a big plus
Post-silicon debug and bench equipment experience
Good communication skills and team player
Linux environment and writing /using scripting languages such as Perl, Tcl, etc.
We invite qualified candidates to apply online or email their CVs to *************
Work closely with design teams and make sure DFT structures are correctly implemented
Responsible for verifying DFT schemes on IPs in ASIC and FPGA products
Responsible for block level and SoC level ATPG and verification with DFT rule check and debug for various testing modes
Responsible for memory tests (MBIST, BISR), IEEE1149.1 JTAG and IEEE1687 iJTAG
Responsible to develop firmware-driven cost-effective test methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench and ATE
Assist test pattern failure debug and diagnosis on FPGA-based test environment and ATE machine through product lifecycle
Main Requirements
Degree in Electrical/ Electronics/ Computer Engineering or equivalent with min 1 year DFT experience
Experience on pre-silicon DFT design specification and scan insertion
Engineering experience on DFT design verification (ATPG/MBIST/simulation)
Tessent Streaming Scan Network (SSN) hand-on experience is a big plus
Post-silicon debug and bench equipment experience
Good communication skills and team player
Linux environment and writing /using scripting languages such as Perl, Tcl, etc.
We invite qualified candidates to apply online or email their CVs to *************
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