- Clementi West Region (Singapore) Singapore
RICORE TECHNOLOGY PTE. LTD. Hiring! Full Time GPU Digital Frontend Design Engineer in West Region (Singapore), Earn up to SGD 10,000 - Ricebowl
GPU Digital Frontend Design Engineer
RICORE TECHNOLOGY PTE. LTD.
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Job Description
Responsibilities
Job Responsibilities
Responsible for requirement analysis, GPU microarchitecture definition, specification drafting and module interface design for high-performance GPU/AI accelerator chips.
Conduct RTL design and PPA optimization for GPU key modules including SIMD Core, Tensor Core, scheduling system, on-chip memory and interconnect network.
Develop synthesizable Verilog/SystemVerilog code and optimize timing, area and power consumption.
Collaborate with verification team on UVM verification plan, environment setup and debug.
Work with algorithm and software teams for operator performance analysis and architecture optimization.
Support logic synthesis, STA, low-power design, physical design co-optimization, FPGA prototyping and post-silicon debug.
Job Requirements
Master’s degree or above in Microelectronics, Electronic Engineering, Computer Science or related fields.
2+ years digital IC frontend design experience; GPU / AI accelerator chip project experience is highly preferred.
Proficient in Verilog/System Verilog; familiar with Python / Tcl / Perl scripting.
Solid understanding of GPU/SoC architecture and low-power design methodology.
Hands-on experience with IC frontend flow and EDA tools: DC, PT, Verdi, Spyglass, LEC.
Responsible for requirement analysis, GPU microarchitecture definition, specification drafting and module interface design for high-performance GPU/AI accelerator chips.
Conduct RTL design and PPA optimization for GPU key modules including SIMD Core, Tensor Core, scheduling system, on-chip memory and interconnect network.
Develop synthesizable Verilog/SystemVerilog code and optimize timing, area and power consumption.
Collaborate with verification team on UVM verification plan, environment setup and debug.
Work with algorithm and software teams for operator performance analysis and architecture optimization.
Support logic synthesis, STA, low-power design, physical design co-optimization, FPGA prototyping and post-silicon debug.
Job Requirements
Master’s degree or above in Microelectronics, Electronic Engineering, Computer Science or related fields.
2+ years digital IC frontend design experience; GPU / AI accelerator chip project experience is highly preferred.
Proficient in Verilog/System Verilog; familiar with Python / Tcl / Perl scripting.
Solid understanding of GPU/SoC architecture and low-power design methodology.
Hands-on experience with IC frontend flow and EDA tools: DC, PT, Verdi, Spyglass, LEC.
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