- Kuala Lumpur Federal Territory Malaysia
HCLTech Hiring! Full Time Senior Physical Design Engineer in Federal Territory - Ricebowl
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Working Location
Job Description
Responsibilities
Kuala Lumpur, Federal Territory of Kuala Lumpur
Job Summary
Perform end‑to‑end physical design flow:
Floorplanning
Power planning (PG grid, IR)
Placement & optimization
CTS (Clock Tree Synthesis)
Routing
Post‑route optimization
Achieve timing closure across all modes and corners
Resolve DRC, LVS, ERC and signoff violations
Handle low‑power design techniques:
Multi‑Vt, Multi‑voltage (UPF)
Power gating, clock gating
Perform physical verification and signoff:
STA (Primetime)
SI / Crosstalk
IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
Collaborate with:
RTL & Micro‑architecture teams
DFT & Test engineers
Foundry and CAD teams
Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)
Key Responsibilities
1. Collaborate With Stakeholders To Gather And Refine Design Requirements, Ensuring That Project Specifications Are Accurately Captured And Addressed.
2. Develop And Validate Prototypes Using Physical Design Tools Such As Synopsys Ic Compiler And Cadence Innovus, Ensuring Design Decisions Meet Performance And Functionality Criteria.
3. Mentor And Guide Junior Designers By Sharing Expertise Through Training Sessions And Creating Detailed Documentation To Enhance Team Knowledge.
4. Work Closely With Cross-Functional Teams, Including Hardware And Software Engineers, To Ensure Alignment Of Physical Design With Overall Project Goals And Objectives.
5. Partner With Quality Assurance Teams To Implement And Maintain Rigorous Testing Processes, Ensuring The Delivery Of High-Quality Designs That Meet Industry Standards.
Skill Requirements
1. Strong Understanding Of Physical Design Methodologies And Tools, Including Knowledge Of Place And Route, Drc, And Lvs Checks.
2. Proficiency In Using Design Software Such As Cadence, Synopsys, Or Mentor Graphics.
3. Familiarity With Semiconductor Design Principles And Practices.
4. Excellent Communication Skills To Effectively Interact With Stakeholders And Team Members.
Other Requirements
1. Optional But Valuable Certifications Include Certified Asic Design Engineer (Cade) And Physical Design Verification Certification.
************* ************* .unify-apply-now: focus, ************* ************* ************* ************* .unify-apply-now: focus, ************* ************* .unify-apply-
Job Summary
Perform end‑to‑end physical design flow:
Floorplanning
Power planning (PG grid, IR)
Placement & optimization
CTS (Clock Tree Synthesis)
Routing
Post‑route optimization
Achieve timing closure across all modes and corners
Resolve DRC, LVS, ERC and signoff violations
Handle low‑power design techniques:
Multi‑Vt, Multi‑voltage (UPF)
Power gating, clock gating
Perform physical verification and signoff:
STA (Primetime)
SI / Crosstalk
IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
Collaborate with:
RTL & Micro‑architecture teams
DFT & Test engineers
Foundry and CAD teams
Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)
Key Responsibilities
1. Collaborate With Stakeholders To Gather And Refine Design Requirements, Ensuring That Project Specifications Are Accurately Captured And Addressed.
2. Develop And Validate Prototypes Using Physical Design Tools Such As Synopsys Ic Compiler And Cadence Innovus, Ensuring Design Decisions Meet Performance And Functionality Criteria.
3. Mentor And Guide Junior Designers By Sharing Expertise Through Training Sessions And Creating Detailed Documentation To Enhance Team Knowledge.
4. Work Closely With Cross-Functional Teams, Including Hardware And Software Engineers, To Ensure Alignment Of Physical Design With Overall Project Goals And Objectives.
5. Partner With Quality Assurance Teams To Implement And Maintain Rigorous Testing Processes, Ensuring The Delivery Of High-Quality Designs That Meet Industry Standards.
Skill Requirements
1. Strong Understanding Of Physical Design Methodologies And Tools, Including Knowledge Of Place And Route, Drc, And Lvs Checks.
2. Proficiency In Using Design Software Such As Cadence, Synopsys, Or Mentor Graphics.
3. Familiarity With Semiconductor Design Principles And Practices.
4. Excellent Communication Skills To Effectively Interact With Stakeholders And Team Members.
Other Requirements
1. Optional But Valuable Certifications Include Certified Asic Design Engineer (Cade) And Physical Design Verification Certification.
************* ************* .unify-apply-now: focus, ************* ************* ************* ************* .unify-apply-now: focus, ************* ************* .unify-apply-
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