UST Hiring! Full Time Design Verification (PCIe) Engineer in Pulau Pinang - Ricebowl

Key Responsibilities

• Develop and execute verification plans for PCIe IP/SoC designs.
• Create and maintain SystemVerilog/UVM-based verification environments, testbenches, and test cases.
• Verify PCIe functionality across various protocol layers and ensure compliance with PCIe specifications.
• Develop constrained-random and directed test scenarios.
• Perform functional coverage analysis, code coverage, and assertion-based verification.
• Debug simulation failures and collaborate with design engineers to resolve functional issues.
• Participate in verification reviews and contribute to continuous improvement of verification methodologies.
• Support regression execution, bug tracking, and verification closure.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience in Design Verification.
• Strong experience with PCI Express (PCIe) protocol verification.
• Excellent knowledge of SystemVerilog and UVM.
• Experience with simulation/debug tools such as VCS, Xcelium, QuestaSim, or similar.
• Good understanding of digital design concepts, RTL, and verification methodologies.
• Experience with scripting languages such as Python, Perl, or Shell is an advantage.
• Strong debugging, analytical, and communication skills.

Preferred Skills

• Experience with SoC verification.
• Knowledge of AXI/AHB or other industry-standard protocols.
• Experience with assertion-based verification (SVA) and functional coverage.
• Familiarity with emulation or FPGA prototyping is a plus.