Infinecs System Hiring! Full Time SOC DFX Scan Engineer in Pulau Pinang, Earn up to MYR 9,748.26 - Ricebowl

This role plays a key part in the SoC DV flow, focusing on tile-level scan insertion, ATPG, and scan pattern simulation, while also supporting post-silicon Scan ATE testing and silicon debug activities. We are looking for a strong team player with solid experience in scan insertion, ATPG, and scan pattern silicon debug. Knowledge of IJTAG, Boundary Scan, and BIST methodologies would be an added advantage.

Responsibilities include (but are not limited to)

• Cutting-edge test strategies study and implementation.
• Responsible for tile level scan insertion, ATPG and scan quality check.
• Responsible for tile level scan drc check, non-scan analysis and test coverage improvement
• Responsible for chip level scan test patterns/vectors generation and verification.
• Co-work with test engineers on Scan ATE patterns bring-up, debugging and failure analysis.

Requirements

• Bachelor's Degree in Engineering, Quality Management, Science or related disciplines.
• Minimum 5 years of experience in DFT, scan insertion, ATPG, scan verification, or silicon debug within semiconductor or SoC design environments.
• Solid background on process, device or ASIC design.
• Strong technical background in scan, SSN and burnin scan.
• Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a plus.
• Good knowledge on DFT Scan/BIST will be a plus.
• Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.
• Good communication skills and self-driven, willing to learn/share.

Pay: RM4,752.43 - RM9,748.26 per month

Experience:

• DFT: 5 years (Preferred)

Work Location: In person