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XILINX ASIA PACIFIC PTE. LTD. Hiring! Full Time Silicon Design Engineer - RTL Integration in Islandwide (Singapore), Earn up to SGD 4,000 - Ricebowl

Silicon Design Engineer - RTL Integration

XILINX ASIA PACIFIC PTE. LTD.

SGD4,000 - SGD4,000 Per Month

Islandwide (Singapore)

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Working Location

  • Islandwide (Singapore) Singapore

Job Description

Responsibilities

THE ROLE:

The role involves integrating RTL components from different design teams into AMD's next generation FPGA and programmable SOC products; building Full-Chip RTL connectivity models; verifying Full-Chip models match architectural intent; and developing custom tools and methodologies to improve development efficiency and quality.

THE PERSON:

We are looking for a highly qualified and driven RTL digital design engineer to join our FPGA Product Development (FPD) Silicon Integration team. The candidate should have a passion for modern, complex processor architecture, digital design, and verification in general. The candidate must be a team player who has excellent communication skills and experience collaborating with team members and other engineers across globally diverse regions. The candidate must also have strong analytical and problem-solving skills; be willing to learn and ready to take on problems; and is a self-starter able to work on his/her own as well as within a team.

KEY RESPONSIBILITIES:

  • Develop Full-Chip SoC RTL
  • Write Full-Chip Design Specification documents
  • Work with IP development teams to integrate IP components
  • Work across Architecture, Software, and Verification teams to assure Full-Chip SoC RTL quality
  • Run lint and other static verification tools

PREFERRED EXPERIENCE:

  • Experience or familiarity using FPGAs
  • Deep understanding of complex FPGA and SoC architectures
  • Proven experience in ASIC design flow execution
  • Proficient in RTL and behavioral coding in Verilog/SystemVerilog HDL
  • Familiarity with CAD tools such as VCS, Verdi, Design Compiler, Primetime, Spyglass,
    Lint, Conformal, CDC/RDC tools, etc.
  • Familiarity in timing constraints for synthesis and STA at SoC level
  • Familiarity in Unix/Linux computing environment and scripting languages such as Shell
    Scripts, Perl, and/or Python
  • Familiarity with Revision Control software such as Perforce

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in Electrical Engineering / Computer Engineering

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