PenguinChip Sdn. Bhd. Hiring! Full Time Senior DV - STA Engineer in Pulau Pinang - Ricebowl

Benefits:

Competitive salary and bonus structure

Comprehensive health insurance plans

Flexible working hours

Opportunities for professional growth and development

Collaborative and innovative work environment

Application Instructions:

Please submit your resume and cover letter to [*************] with the subject line“Name-Position Applied For”

Ⅰ.DV Position：

Responsibilities:

1.Candidate should be able to work independently on various DV task and providing technical

guidance to DV team.

2.Collaborate with architects, hardware engineers, and firmware engineers to understand the new

features to be verified.

3.Build test plan documentation, accounting for interactions with other features, the hardware, the

firmware, and the software driver use cases.

4.Estimate the time required to write the new feature tests and any required changes to the test environment.

5.Build the directed and random verification tests.

6.Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.

7.Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

EXPERIENCE:

1.Proficient in IP/SoC level ASIC verification.

2.Proficient in debugging firmware and RTL code using simulation tools.

3.Proficient in using UVM testbenches and working in Linux and Windows environments.

4.Strong background with UVM, Verilog, System Verilog, C, and C++ .

5.USB,UFS,Ethernet,PCIE,AXI knowledge is a plus.

6.Developing UVM based verification frameworks and testbenches, processes and flows.

7.Automating workflows in a distributed compute environment.

8.Exposure to power aware simulations is a plus.

9.Good understanding and hands-on experience in the UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)

10.Good working knowledge of SystemC and TLM with some related experience.

11.Scripting language experience: Perl, Ruby, Makefile, shell preferred.

12.Exposure to leadership or mentorship is an asset.

13.3-15yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry.

Ⅱ.STA Position

Responsibilities:

1.The scoping includes synthesis, formality check, low power check and full-chip SDC

generation. Need work in big and complex with advanced process and technology.

2.Knowledgeable in all aspects of ASIC design flow.

3.Familiar with EDA tools.

4.Good leadership skills.

5.Good teamwork and script skills.

6.Good training skills to ramp-up new team members.

RESPONSIBILITIES:

1.Do working assignment for team members, tracking and supporting for critical problems.

2.Co-work with IP/DFT/PD team to improve timing/area/power during synthesize.

3.Netlist quality check including EQV/LowPower/Timing.

4.Generate full-chip level SDC and SDC quality check.

EXPERIENCE:

1.Synthesize experience by DC/DC-NXT/Fusion-Compiler.

2.EQV debug experience by FM/LEC.

3.Low power check experience by VC-LP.

4.Static Timing Analysis experience by PT.

5.Power Analysis experience by PTPX.

6.Good at scripts, like Python/perl/Tcl/Shell.

7.Language proficiency: Mandarin and English.