UST Hiring! Full Time Design Verification Engineer (IP Level - Formal Focus) in Pulau Pinang - Ricebowl

Key Responsibilities

• IP-Level Verification Planning: Analyze IP specifications and microarchitectural documents to define comprehensive verification strategies, mapping out which blocks require formal proofs and which require constrained-random testbenches.
• Formal Property Development: Develop explicit SystemVerilog Assertions (SVA) to mathematically prove corner-case control logic, state machines, and interface protocols within the IP.
• UVM Testbench Ownership: Build, maintain, and run block-level testbenches using SystemVerilog and UVM to verify deep data paths and complex traffic patterns.
• Proof Convergence Optimization: Set up design assumptions, constraints, and custom abstractions to guide formal tools away from state-space explosion and achieve full mathematical convergence.
• Block-Level Closure: Drive block-level sign-off by achieving 100% code coverage, functional coverage, and assertion coverage.
• RTL Triage: Work closely with the IP RTL design owner to debug block-level failures, root-cause design issues, and refine microarchitectural boundaries for better testability.

Required Experience and Technical Skills

• Experience: 2 to 6 years of industry experience specializing in IP block-level digital design verification.
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Formal EDA Tools: Practical experience with commercial formal verification software (e.g., Cadence JasperGold, Synopsys VC Formal, or Siemens OneSpin).
• Languages & Standards: Expert command of SystemVerilog, SVA, and UVM architecture (monitors, drivers, scoreboards, and sequencers).
• Scripting: Proficiency in Python, Tcl, or Perl for managing automated block-level regression runs and parsing logs.
• Technical Fundamentals: Solid understanding of hardware design concepts like clock domain crossing (CDC), asynchronous FIFOs, arbiters, and pipeline dependencies.

Preferred Qualifications (Nice to Have)

• Direct experience writing formal properties for standard IP interfaces like AMBA (AXI, AHB, APB) or tilelink.
• Familiarity with Formal Scoreboarding for data integrity verification.
• Knowledge of power management verification (UPF) at the IP level.