OMNIVISION Hiring! ASIC DFT IP Development Intern in West Region (Singapore) - Ricebowl

Commitment Period: Jan 2027 onwards (Full-time Internship, min. 6 months)

Join our DFT IP Development team to design and verify digital built-in self-test (BIST) IP for mixed-signal ASICs. You will contribute to a defined engineering project with guidance from DFT, analog design and product test engineers.

Key Responsibilities:

• Develop synthesizable SystemVerilog RTL for digital test control and result reporting.
• Build self-checking testbenches, run simulations and debug design and verification issues.
• Support interface definition, IP integration, lint, synthesis and clock-domain-crossing checks with your mentor.
• Investigate analog defect modeling and coverage using IEEE 2427, and evaluate improvements to test coverage and efficiency.
• Document design decisions and results, participate in technical reviews and present your findings to the team.

Required Qualifications:

• Pursuing a master’s degree in electrical engineering, computer engineering, microelectronics or a related discipline.
• Coursework or project experience in digital logic design and simulation using Verilog or SystemVerilog.
• Understanding of state machines, clocks, resets and basic analog circuit concepts.
• Strong analytical skills and the ability to explain and document technical work clearly.

Preferred Qualifications:

• Exposure to ADCs, DACs, analog circuit simulation or mixed-signal modeling.
• Familiarity with SystemVerilog assertions, UVM or ASIC design tools.
• Experience with Python scripting or semiconductor test.

Mentorship and Learning:

• Weekly mentoring and design reviews, with feedback at the midpoint and end of the internship.
• Practical experience taking a DFT IP project from specification through RTL implementation, verification and technical evaluation.

Application Materials

• Submit your CV, academic transcript and a brief description of a digital design project. A code sample or project report is welcome.