Bachelor's degree or above in Electronic Information, Microelectronics or related majors, with 3-5 years of relevant experience in debugging AMD laptop boards.
Proficient in hardware bring up and software tools, possess solid fault analysis capabilities.
Skilled in using test instruments such as logic analyzers, master signal and system level integrity knowledge, and be able to independently complete complex fault location.
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Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure and debugging in accordance with functional safety requirements.
Demonstrate technical ownership of safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.
Working knowledge of any FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features is a plus.
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• Lead test software and test script development based on product requirements and test plans.
• Drive Design for Testability (DFT) reviews with customers, R&D, and hardware design teams during all NPI phase gates to ensure adequate test coverage, fault isolation capability, and manufacturability.
• Provide DFT recommendations on hardware architecture, debug interfaces, test access points, boundary scan (JTAG), and diagnostic capabilities to optimize production testing and failure analysis.
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