全职 Sub-system Integration Verification Engineer 工作, 薪水, PenguinChip Sdn. Bhd. Pulau Pinang 公司招聘中 - Ricebowl

Subsystem Integration Verification Engineer

Responsibilities

1. Verification planning: Develop a subsystem-level verification plan, scenario matrix, and coverage goals based on the IO architecture and interface specifications. Align interface contracts and ownership boundaries with each IP owner.
2. Environment and VIP integration: Build or reuse a UVM subsystem verification environment. Resolve coordination issues involving timing and stimulus across multiple VIPs, clock domains, and reset domains.
3. Scenario development and execution: Design and implement cross-IP scenarios, including:

• Configuration-space enumeration and BAR decoding
• MSI/MSI-X interrupt aggregation and routing
• Hot-plug and presence detection
• Power-state transitions involving D0/L1/L2/L3 and D3hot/D3cold
• Injection and containment of errors such as AER, poison, and timeout
• QoS and ordering under concurrent access by multiple IPs

1. Coverage closure and sign-off: Close functional, code, and assertion coverage; add formal analysis and directed tests as needed. Manage regressions, classify failures, and track defects through subsystem-level sign-off.
2. Issue triage and cross-functional resolution: Distinguish integration issues from IP-level defects, quickly isolate the affected interface or boundary, and drive resolution with the responsible teams. Collaborate with design, IP DV, firmware, and emulation/FPGA teams to reproduce and close issues.
3. Boot-flow coordination: Work with BIOS/firmware teams (AGESA/ABL) to verify enumeration and initialization sequences, and participate in boot-flow validation on emulation/FPGA platforms.

Qualifications

• Bachelor’s degree or above in Electrical Engineering, Microelectronics, Computer Engineering, or a related field.
• At least 3 years of IC verification experience; 8+ years for a senior-level position.
• Strong SystemVerilog and UVM skills, with the ability to independently build or modify a subsystem-level verification environment.
• Experience integrating VIPs and familiarity with at least two of the following: PCIe, AXI, AHB, or APB.
• Familiarity with the PCIe protocol stack—including TLP, configuration space, AER, and power management—or another high-speed I/O protocol.
• Understanding of clocks, resets, and CDC; able to interpret timing diagrams and state machines and quickly debug interactions across multiple clock domains.
• Proficiency in Python and/or Shell scripting, and experience using Git and CI for automated regressions.

Preferred Qualifications

• Project experience with PCIe Root Complex, IOMMU, or ATS.
• Emulation experience with Palladium or Zebu, or FPGA prototyping and verification experience.
• Post-silicon bring-up and lab-debug experience using tools such as protocol analyzers and oscilloscopes.
• Experience developing VIP, maintaining verification IP, or establishing verification methodologies.