全职 ASIC Front-End Integration Engineer (RTL, Synthesis, CDC, LEC, UPF) 工作, 薪水, UST Malaysia Pulau Pinang 公司招聘中 - Ricebowl

We are seeking a Front End Integration Engineer to perform IP-level FE Integration (FEInt) tasks. The ideal candidate will have expertise in synthesis, linting, CDC (Clock Domain Crossing), LEC (Logical Equivalence Checking), UPF (Unified Power Format), and related front-end implementation and verification methodologies. Exposure to Physical Design (PD) and Static Timing Analysis (STA) flows is highly desirable.

Responsibilities

• Conduct synthesis and optimization of IP blocks
• Perform linting to ensure code quality and adherence to design guidelines
• Conduct CDC analysis to identify and address potential clock domain crossing issues.
• Perform LEC to ensure design consistency before and after synthesis
• Implement UPF methodologies for power-aware design and low-power verification
• Collaborate with verification, architecture, and backend teams to ensure seamless IP integration and handoff

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Qualification

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• At least 3 years of experience in Front End Integration (FEInt) tasks
• Strong expertise in synthesis, linting, CDC, LEC, and UPF methodologies
• Proficient in industry-standard EDA tools
• Rich verification experience (block-level or SoC-level); simulation and formal verification experience are additional advantage
• Good understanding of RTL design and SystemVerilog
• Proficiency in scripting languages such as Perl, Python, or TCL. UVM and verification experience are considered an advantage
• Strong debugging capabilities with hands-on experience in VCS, Verdi, and DVE tool
• Familiarity with standard AMBA/AXI/AHB interface protocols.
• Strong problem-solving, analytical, communication, and teamwork skill

Preferred Qualification

• Knowledge of Physical Design (PD) flows, including floorplanning, place-and-route, power planning, and timing closure concepts
• Experience with Static Timing Analysis (STA) and timing sign-off methodologies
• Familiarity with front-end and back-end design handoff process
• Understanding of timing constraints development and timing/debug analysis
• Experience working with advanced-node ASIC/SoC development flows is an advantage