- Singapore
全职 Senior- IC Design Engineer (Design Verification) 工作, 薪水 up to SGD 10,000, AUREXIS TECH PTE. LTD. 公司招聘中 - Ricebowl
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Job Description
Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
Build and maintain SystemVerilog/ UVM-based verification environments and testbenches
Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
Debug DUT issues, analyze simulation results, and drive verification closure.
Collaborate with cross-functional teams throughout the design and verification lifecycle.
Support regression automation and continuously improve verification methodologies.
Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.
Requirements
Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field with at least 1 year of experience.
Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM.
Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
Experience with industry-standard EDA tools (e.g., Cadence or Synopsys).
Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
Strong analytical, problem-solving, and communication skills.
We invite qualified candidates to apply online or submit a detailed resume to *************
.
Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
Build and maintain SystemVerilog/ UVM-based verification environments and testbenches
Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
Debug DUT issues, analyze simulation results, and drive verification closure.
Collaborate with cross-functional teams throughout the design and verification lifecycle.
Support regression automation and continuously improve verification methodologies.
Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.
Requirements
Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field with at least 1 year of experience.
Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM.
Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
Experience with industry-standard EDA tools (e.g., Cadence or Synopsys).
Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
Strong analytical, problem-solving, and communication skills.
We invite qualified candidates to apply online or submit a detailed resume to *************
.
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