Translate AI inference workloads into measurable architecture requirements and implementable accelerator designs
Responsibilities:
- Characterize Transformer inference workloads, including attention, feed-forward layers, prefill, and decoding; identify compute, memory, bandwidth, and latency bottlenecks.
- Build reproducible performance and capacity models to compare dataflows, tiling strategies, memory hierarchies, and compute microarchitectures.
- Evaluate architectural trade-offs using simulation or analytical methods
- Mapping LLM into hardware
- Work with compiler, RTL, verification, and physical design teams to define interfaces, implementation constraints, and validation cases
Required Qualifications:
- Bachelor's degree or above in computer engineering, computer science, electrical engineering, or a related field.
- Knowledgeable in computer architecture, such as AI Accelerator, CPU, network-on-chip, memory hierarchy
- Familiarity with LLM inference, quantization, compiler mapping, is a plus
- Strong learning capability, good communication and collaboration skills
- Experience with AI accelerators, GPUs, or hardware-software co-design is a plus
Preferred Qualifications:
- Projects involving AI workloads, accelerator kernels, or compiler tools
- Exposure to performance modeling, quantization, or hardware interfaces
Growth opportunities:
- Opportunities to shape the leading-edge AI chip architecture
- Learn quantitative methods for evaluating throughput, latency, memory traffic, and numerical trade-offs