全职 Foundry Engineer - Sr 工作, 薪水, InvenSense 台灣 公司招聘中 - Ricebowl

Overview/Job Summary

The Sr. Foundry Engineer acts as the primary technical interface between internal cross-functional teams and external wafer foundry partners. This role is responsible for driving silicon yield improvement, establishing robust quality gating, managing process excursions, and collaborating deeply with foundries on device physics, process integration, and SPC.

Job Description

1. Yield Learning & Continuous Improvement

• Yield Analysis: Lead systematic yield analysis across various technology nodes (e.g., 0.18µm, 0.11µm, 55nm).
• Root Cause Isolation: Identify systematic and random yield detractors using parametric data (PCM/WAT), inline defect monitoring, EFA/FA correlation, and Layout-Dependent Effects (LDE).
• Experimental Design: Coordinate DOE with foundries to validate corrective actions.
• NPI Management: Establish yield baselines, monitor DPPM/bin splits, and set learning rate targets for New Product Introductions.

2. Quality Gating & Process Control Governance

• Quality Criteria: Define wafer acceptance criteria based on PCM specs, inline defect thresholds, and reliability monitors (HTOL, EM, TDDB, BTI).
• Excursion & Risk Management: Lead MRB, audit foundry SPC control plans/OCAPs, and drive robust 8D closure.
• Risk Frameworks: Implement FMEA frameworks to ensure a zero-escape strategy across wafer sort and final test.

3. Foundry Technical Engagement

• Technical Escalation: Act as the primary technical interface with major foundries (e.g., TSMC, UMC, GlobalFoundries).
• Process Optimization: Engage with foundry integration and module teams (FEOL/BEOL, Litho, Etch, CMP) to optimize process windows and align specs.
• Change Management: ReviewPCN, assess silicon impact, and lead Quarterly Technical Reviews (QTR).

4. Technology Qualification & Risk Mitigation

• Node Qualification: Support technology node qualification, transfers, and dual-sourcing strategies.
• Validation Matrices: Define qualification matrices for new mask sets, ECOs, and die shrinks.
• Reliability Monitoring: Evaluate the silicon impact of material changes, tool matching, and long-term degradation mechanisms.

5. Cross-Functional Leadership

• Collaboration: Bridge the gap between Design, Product, Test, and Reliability teams to translate silicon failures into actionable design or process fixes.
• Mentorship: Guide junior engineers in yield methodologies and foundry engagement strategies.
• Reporting: Present high-level yield dashboards and technical summaries to executive leadership.

Qualifications

• Education: MS in Electrical Engineering, Materials Science, Physics, or a related field.
• Experience: 3+ years of solid experience in Semiconductor Foundry operations, PIE, or Yield Enhancement (YE).
• Technical Expertise:
  • Deep understanding of semiconductor manufacturing processes (CMOS, MEMS, CMOS/MEMS integration, specialized motion/inertial sensor key steps).
  • Familiarity with WAT parameters, CP yield data, and electronic circuits.
• Data Analytics: Proficiency in data analysis tools such as JMP, Python, SQL, or equivalent.
• Language & Communication: Strong English communication skills (written and verbal) are highly preferred, with a proven ability to lead technical meetings and drive alignment with international partners.

InvenSense, a TDK group company, is a world-leading provider of MEMS and magnetic sensor solutions found in mobile, wearable, smart home, AR/VR, and other consumer and IoT applications. We are innovators with a 20+ year history of patented sensor technologies. As experts in our field, we lead industry breakthroughs in consumer, industrial and automotive technology and reliably deliver high-quality solutions to our partners across global markets. Learn more about us at *************