Working experience with 16nm and more advanced technology
Experience in Cadence Virtuoso, Calibre Verification (DRC, LVS) prefferred.
Familiar with Analog Custom Layout : PLL, Amplifier, DLL
Hand on experience in memory compilers / SRAM / RAM / ROM is a plus
Comprehensive understanding of the targeted process to balance layout and circuit design needs, e.g. Crosstalk, RC delay, Electro-migration, IR drop, self-heating, shielding, matching, guard rings and latch-up.
Responsibilities :
Play a key role in the development of innovative analog and digital layout ( floor planning, device placement, matching and routing, LVS, DRC, DFM check and reliability verification ) and solving technical issues in different process technologies.
Cooperate with Design Lead, Circuit designers, and Layout engineers to implement custom IPs and archive full chip integration, place and route, top level verification and tape out.
Responsible for layout optimization, post layout extraction and parasitic analysis.
Guide and coach juniors by ensuring their works meets the desired area, performance and power consumption.
Education & Experience :
Bachelor or Master degree in E&E or Computer Engineering.