8 CLEANTECH LOOP West Region (Singapore) Singapore
职位描述
岗位职责
Responsibilities:
Convert design specification documents into layout designs
Perform layout design from lower-level modules to top-level placement, routing, and verification
Communicate closely with design engineers to fully understand layout requirements, assist in layout floor planning/design, and complete layout design for circuit modules and full-chip integration
Develop layout design guidelines and checklists for layout inspection, verification, and design documentation archiving;
Handle project tape-out activities
Other ad-hoc tasks as assigned by supervisors
Requirements:
Bachelor’s Degree in Microelectronics, Electronic Engineering, or related fields;
Minimum 1 year of experience in semiconductor industry
Proficient in reading and understanding Foundry process flow and design rule documents, fully understand the device structures of the process technology used, and establish standard cell libraries;
Experience with Python for layout design
Experience in writing Calibre DRC runset scripts
Experience or knowledge with the Tape-Out process are preferred.