全职 Technical Staff Engineer - Design 工作, 薪水 up to MYR 20,000, Agensi Pekerjaan Shivz Solution Pulau Pinang 公司招聘中 - Ricebowl

We are seeking a highly skilled Technical Staff Engineer - Design to lead ASIC design implementation activities from architectural understanding through RTL-to-GDS execution and timing signoff. The successful candidate will drive design implementation excellence, support advanced technology nodes, and contribute to methodology improvements for successful tape-outs.

Responsibilities:

ASIC Design Implementation

• Lead ASIC design implementation activities from RTL synthesis to timing signoff and tape-out.
• Develop and improve RTL-to-GDS implementation flows and methodologies.
• Understand architectural and micro-architectural design intent to ensure successful implementation.
• Optimize RTL structures for efficient synthesis and physical design convergence.
• Develop, review, and validate timing constraints with designers and architects.
• Drive Design-for-Test (DFT) implementation, including scan insertion, compression, LOC/LOS, RAM BIST, and advanced DFT optimization techniques.
• Support low-power design methodologies, including power-aware optimization, leakage reduction, and dynamic power control techniques.
• Provide technical leadership, mentoring, and guidance to team members in resolving complex implementation challenges.
• Contribute to innovation through patents, technical publications, and proprietary design methodologies.
• Benchmark and drive best-in-class ASIC implementation methodologies and processes.

Documentation & Process Compliance

• Document implementation methodologies, design considerations, challenges, and solutions using company standards.
• Complete design audits, reviews, and compliance checklists in accordance with corporate Design Control Procedures (DCP).
• Maintain accurate records of issues, resolutions, and design reviews within PEPS, JIRA, or other project management systems.

Cross-Functional Collaboration

• Work closely with Project Managers, Design Engineers, ATPG, DFT, and Product Development teams.
• Collaborate with CAD and Technical Application (TA) teams on flow enhancements and methodology improvements.

Requirements

• Bachelor's or Master's Degree in Electrical/Electronics Engineering or a related discipline.
• 8 to 12 years of hands-on experience in ASIC Physical Design or Design Implementation.
• Strong expertise in:
• Cadence Genus or Synopsys Design Compiler
• Cadence Tempus or Synopsys PrimeTime
• Proven experience in synthesis, timing closure, and timing signoff.
• Strong understanding of ASIC implementation methodologies, timing constraints, and optimization techniques.
• Excellent analytical, troubleshooting, and problem-solving skills.
• Strong communication and technical leadership capabilities.

Added Advantage

• Experience with advanced process nodes (7nm and below).
• Familiarity with SystemVerilog coding and RTL design concepts.
• Strong scripting skills in Perl, Tcl, Shell, or Python.
• Experience with low-power design methodologies (UPF/CPF).
• Exposure to place-and-route, physical verification, and signoff flows.

Pay: RM18,500.00 - RM20,000.00 per month

Work Location: Hybrid remote in Bayan Lepas