全职 IC Logic Design Engineer (STA) 工作, 薪水 up to SGD 9,387.95, Flamingo Recruitment Singapore Central Region (Singapore) 公司招聘中 - Ricebowl

Location: Somerset, Singapore
Job Type: Full-time

About the Role

We are looking for an experienced IC Logic Design Engineer specializing in Static Timing Analysis (STA) to join our growing IC design team in Singapore. You will own timing closure across the design flow, working closely with front-end and back-end teams to deliver high-quality silicon.

Key Responsibilities

• Perform logic synthesis, logic equivalence checking (LEC), ECO implementation, and quality control throughout the IC development process
• Work closely with front-end design teams to develop and refine timing constraints and drive timely timing closure
• Execute full-chip Static Timing Analysis (STA) and ensure the quality and accuracy of timing constraints
• Collaborate with back-end design teams to complete timing analysis and sign-off

Requirements

• Bachelor’s degree or above in Computer Engineering, Electrical/Electronic Engineering, Communications Engineering, or a related field
• 8+ years of relevant experience in the IC design industry
• Strong knowledge of SDC, with hands-on experience using Design Compiler (DC), Formality, and PrimeTime (PT)
• Solid TCL scripting skills
• Strong understanding of logic synthesis, STA, timing constraints, and timing closure

How to Apply

Interested candidates are invited to apply through Indeed with an up-to-date resume. Only shortlisted candidates will be contacted.

Pay: $5,476.30 - $9,387.95 per month

Work Location: In person