全职 FPGA Design Engineer 工作, 薪水, UST Pulau Pinang 公司招聘中 - Ricebowl

We are seeking an experienced Senior FPGA/RTL Design Engineer with strong technical expertise in RTL design, VHDL, Verilog, Java, C, and hands-on experience with FPGA devices and tools. The ideal candidate will design, develop, verify, and optimize digital hardware architectures for high-performance embedded and hardware systems.

Key Responsibilitie

sFPGA / RTL Desig

• nDesign, and implement RTL modules using VHDL and Verilog
• .Develop FPGA-based solutions using Quartus Prime design tools
• .Perform timing analysis, synthesis optimizations, and resource utilization improvements
• .Integrate, simulate, test, and debug FPGA designs in both pre-silicon and lab environments

.Verification & Validatio

• nCreate and execute testbenches and verification plans for module- and system-level functionality
• .Use simulation tools (ModelSim, QuestaSim) to validate RTL behavior
• .Perform hardware bring-up, debugging, and validation using oscilloscopes, logic analyzers, and SignalTap

.Software / Firmware Integratio

• nDevelop embedded software tools or scripts using C and Java
• .Collaborate with firmware and software teams to ensure seamless integration of FPGA-based components

.Documentation & Collaboratio

• nPrepare detailed design specifications, documentation, and test reports
• .Work closely with cross-functional teams
• .Mentor junior engineers in RTL design methodologies

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Required Qualificatio

• nsBachelor’s or Master’s Degree in Electrical Engineering or related fiel
• d.5+ years hands-on experience in FPGA design, RTL development, and digital logi
• c.Strong proficiency in VHDL, Verilog, and RTL methodologie
• s.Experience with FPGA platforms such as Cyclone, Arria, Strati
• x.Skilled in Quartus Prime, ModelSim/QuestaSim, and timing analysis tool
• s.Programming experience in C and Jav
• a.Strong debugging and problem-solving skill
• s.Excellent communication and teamwork abilitie