Digital Implementation Engineer (STA)
Location: Somerset, Singapore (a short walk from Somerset MRT Station, Orchard area)
Job Type: Full-time, Permanent
About the Role
We are looking for a Digital Implementation Engineer with strong STA expertise to join our growing IC design team in Singapore. You will build and optimize the synthesis, formal verification and STA flows, and own timing closure from constraints through to sign-off, working closely with front-end and back-end teams.
Key Responsibilities
- Develop, maintain, and optimize flows for logic synthesis, formal verification, and STA, ensuring quality, accuracy, and efficiency
- Develop and review module-level and full-chip SDC timing constraints with front-end design teams
- Execute full-chip STA, identify timing issues, and drive timing closure
- Implement timing ECOs and collaborate with front-end and back-end teams to resolve timing-related issues
Requirements
- Bachelor’s degree or above in Electronic Information Engineering, Microelectronics, IC Engineering, AI, or a related field
- Strong Verilog and SDC skills, with a solid understanding of synthesis, formal verification, STA, and timing closure
- Hands-on experience with EDA tools for synthesis, formal verification, and STA
- Proficiency in TCL, Perl, and Python; strong flow automation skills are a plus
- Strong analytical, problem-solving, communication, and teamwork skills, with a proactive and ownership-driven mindset
Nice to Have
- Experience with formal verification debugging, timing ECOs, and full-chip STA
- Familiarity with DFT, including BIST, SCAN, JTAG, and ATPG
How to Apply
Interested candidates are invited to apply through Indeed with an up-to-date resume. Only shortlisted candidates will be contacted.
Pay: $6,258.63 - $10,170.27 per month
Work Location: In person