全职 Design Verification Engineer 工作, 薪水, Axcellence Consulting Pulau Pinang 公司招聘中 - Ricebowl

Key Responsibilities

• Develop, maintain, and optimize RTL designs using Verilog/SystemVerilog for ASIC/SoC products.
• Contribute to architecture definition, microarchitecture development, RTL implementation, and system integration.
• Develop UVM-based verification environments, test plans, test cases, SystemVerilog Assertions (SVA), and functional coverage models.
• Debug functional, performance, and integration issues across IP, subsystem, and SoC levels.
• Design and develop AI agents and copilots to enhance RTL design, verification, debugging, code review, and engineering productivity.
• Apply Generative AI, Large Language Models (LLMs), and agentic AI technologies to automate RTL analysis, test plan and assertion generation, coverage analysis, debug triage, and regression failure root-cause analysis.
• Build AI-powered engineering workflows using Python, LangChain, MCP tools, vector databases, and modern GenAI platforms.
• Collaborate with cross-functional teams, including Architecture, Design, Design Verification (DV), Physical Design, Emulation, Post-Silicon, and Software Engineering, to identify and implement high-impact AI use cases.
• Drive AI adoption across silicon engineering teams by developing reusable frameworks, sharing best practices, and establishing effective methodologies.
• Mentor engineers in AI-assisted design and verification practices, and evaluate the productivity improvements achieved through AI-enabled solutions.

Requirements & Qualifications

• Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related discipline
• Minimum 3 years of experience in ASIC/SoC RTL Design and/or Design Verification.
• At least 1 year of hands-on experience applying AI/ML or Generative AI technologies.
• Strong proficiency in Verilog/SystemVerilog and RTL design methodologies.
• Solid understanding of ASIC/SoC development flows, UVM-based verification, functional coverage, and SystemVerilog Assertions (SVA).
• Practical experience with Generative AI, LLMs, prompt engineering, and AI agent workflows.
• Strong Python programming skills, with experience in Linux, Git, and scripting automation.
• Familiarity with Retrieval-Augmented Generation (RAG), Model Context Protocol (MCP), and AI development frameworks such as LangChain, LangGraph, AutoGen, or CrewAI.
• Familiarity with cloud-based AI platforms and AI-assisted software development tools.
• Strong analytical, problem-solving, and debugging skills.
• Excellent cross-functional communication and collaboration skills, with the ability to work effectively in multi-site teams and manage multiple priorities.