全职 Design for Test (DFT) Engineer 工作, 薪水 up to SGD 6,000, ALPHAEUS PTE. LTD. 公司招聘中 - Ricebowl

Job Summary

Provide Design for Test (DFT) implementation, verification and engineering support for semiconductor IP, ASIC and System-on-Chip (SoC) projects, from pre-silicon development through post-silicon test debugging.

Key Responsibilities

Analyse project requirements and develop DFT implementation and validation methodologies for semiconductor IP and SoC designs.

Implement and verify scan insertion, scan chain architecture, scan compression and DFT design rule checks.

Generate and validate Automatic Test Pattern Generation (ATPG) patterns for stuck-at, transition, at-speed and path-delay testing.

Analyse fault coverage, investigate coverage gaps and optimise test patterns and test execution time.

Implement and support Memory Built-In Self-Test (MBIST), Memory Built-In Self-Repair (MBISR), hierarchical DFT, IEEE 1500 wrappers and Test Access Mechanisms (TAM).

Perform DFT simulations, timing-aware verification and test pattern debugging.

Work with RTL, physical design, verification and client engineering teams to resolve DFT integration and implementation issues.

Support semiconductor IP integration into customer DFT and production ATPG environments.

Investigate post-silicon test failures by correlating tester results with pre-silicon simulation data.

Evaluate trade-offs involving test coverage, execution time, design area, power and timing.

Develop and maintain scripts to automate DFT flows, validation, log analysis and reporting.

Prepare DFT specifications, validation reports, coverage analyses and project documentation.

Recommend improvements to DFT methodologies and engineering workflows.

Requirements

Bachelor’s or Master’s Degree in Electrical Engineering, Electronics, Microelectronics, Computer Engineering or a related discipline.

5–6 years of relevant hands-on experience in DFT implementation and verification for ASIC, semiconductor IP or SoC designs.

Strong knowledge of scan insertion, scan compression, ATPG, DFT rule checking, fault simulation and coverage analysis.

Experience with MBIST, MBISR and hierarchical DFT methodologies.

Familiarity with JTAG (IEEE 1149.1), IJTAG (IEEE 1687), IEEE 1500 wrappers and test access architectures.

Hands-on experience with relevant EDA tools, such as Siemens Tessent or Cadence Modus, and simulation or debugging tools such as Xcelium, Synopsys VCS or Verdi.

Proficiency in Tcl scripting, with working knowledge of Python or Bash for automation.

Working knowledge of Verilog or SystemVerilog.

Understanding of scan timing constraints, timing-aware simulation and DFT impacts on area, power and performance.

Ability to debug implementation issues, analyse simulation results and investigate silicon test failures.

Strong analytical, documentation, communication and teamwork skills.