全职 IP RTL Integration Engineer 工作, 薪水, UST Pulau Pinang 公司招聘中 - Ricebowl

KEY RESPONSIBILITIES:

• Convert chip spec to RTL using internal and external IPs
• Plan/deliver IP level RTL, and implement front-end RTL integration
• Experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies.
• Knowledge in frontend design experience on IPs involve processor based sub-system, Serial Standard interfaces, Memory controllers
• Exposure to Low-power design, System Security considered as added advantage
• Hands on front-end design of complex multi clock domain blocks
• Fluency in design & verification languages such as VHDL, Verilog, and System Verilog.
• Good in scripting, ie. TCL, shell script, Perl, Python
• Experience in Spyglass for lint and CDC checks.
• Experience in synthesis and LEC flow.
• Experience in identifying and implementing complex ECO in netlist.
• Defining and debugging SDC timing constraints.
• Knowledge on Verification Methodologies to actively participate in Debug Analysis.
• Knowledge about system level flows and interaction with Firmware and Software would be added advantage.
• Optimize the design to meet power, performance, area and timing requirements
• Write easily readable and synthesizable Verilog RTL
• Run unit level testing to deliver quality code to the Design Verification Team
• Create assertions to improve coverage and cover points to analyze coverage of the design
• Create well written block level design documentation
• Self-driven and capable for independent work and independent decision making.

PREFERRED EXPERIENCE:

• Hands on experience in RTL coding required, including IP RTL integration
• Strong understanding of SOC like clocking, reset, boot and power management flows, low power design techniques, security
• Expertise with quality checks like CDC, Lint, VCLP, LEC
• Strong technical engineer who communicates well with great collaboration skills
• Experience in RISC-V, NOC, DMA, bus interfaces ie. APB, AHB, AXI, OBI
• Experience in IPs like PCIe & DDR4/5 will be an advantage
• Experience in packet processing, wireless protocols etc.
• Experience in wireless, base station protocols will be helpful (CPRI, JESD, Uplink/Downlink) would be helpful.