Job Description
The MediaTek Physical Verification team is seeking a qualified candidate to help define and deliver physical sign-off flows and solutions for SoC design, with a focus on enabling technology at advanced process nodes. What you will do:
- Co-work with various teams (PDK, DFM, MF, Designers) to code and maintain DRC/LVS/ANT/DMY/ERC/LPE/ESD rule deck for various processes
- Develop layout implementation flow and physical verification flow
- Co-work with QA team to reduce the PDKs/Rule deck defects
- Perform full-chip physical verification such as debugging DRC/LVS/ERC
- Implement automation scripts in C-shell, Python and Perl
- Explore and apply AI techniques (e.g., LLM-assisted script generation) to improve DRC/LVS/ERC rule deck development, defect triage, and overall physical verification productivity
Main Requirements and Qualifications
- What you will bring:
- Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
- Familiar with IC Design front-to-backend flow
- Preferably well-versed in Calibre, ICV
- Proficient in script programming, such as, Tcl, Perl or C-shell
- Proficient in UNIX (Linux) platforms
- Experience or strong interest in applying AI or LLM-based tools to EDA/CAD automation (e.g., AI-assisted coding, intelligent rule-deck debugging, anomaly detection in verification data) is a plus
- Strong communication skills, problem solving and analytical skills