全职 Serdes Layout Engineer 工作, 薪水, Fusion Semiconductor Pulau Pinang 公司招聘中 - Ricebowl

Company Description Fusion Semiconductor (FusionSemi) is an IC design services company specializing in custom semiconductor solutions for advanced, high-performance applications. With a global team of experienced engineers and consultants, FusionSemi delivers end-to-end design services, including AMS and RF circuit and layout design, as well as physical design, tailored to each client’s requirements. The company partners with industry leaders to drive next-generation technologies in industrial systems, automotive, 5G, and satellite communications. Headquartered in Australia, FusionSemi supports clients worldwide with innovative and impactful semiconductor IC design solutions.

Role Description This full-time, on-site Serdes Layout Engineer role is based in Penang, Malaysia. The Serdes Layout Engineer is responsible for implementing and optimizing high-speed Serdes block layouts, including floorplanning, device placement, routing, and parasitic management to meet performance, area, and reliability targets. Day-to-day tasks include collaborating closely with circuit design engineers to interpret schematics, performing layout-versus-schematic (LVS) and design rule check (DRC) verification, and iterating layouts for signal integrity and power integrity improvements. The role involves working with process design kits (PDKs), preparing documentation and layout reviews, and supporting tape-out activities across multiple process nodes. The engineer will also contribute to layout best practices, design reuse, and continuous improvement of internal layout methodologies and tools.

Qualifications

• Strong skills in analog/mixed-signal layout, particularly Serdes, high-speed I/O, and associated blocks; ability to interpret complex schematics and translate them into robust layouts.
• Hands-on proficiency with industry-standard layout and verification tools (e.g., Cadence Virtuoso, Synopsys, Mentor/Siemens tools) and PDKs for advanced CMOS or FinFET technologies.
• Experience with LVS, DRC, EM/IR, and reliability checks, and familiarity with layout optimization for signal integrity, noise, matching, and electrostatic discharge (ESD) structures.
• Knowledge of high-speed design concepts, including differential signaling, clock distribution, power/ground routing, shielding, and layout techniques for minimizing jitter and crosstalk.
• Understanding of semiconductor manufacturing processes and design-for-manufacturability (DFM) practices relevant to Serdes and mixed-signal circuits.
• Effective communication and collaboration abilities, including working closely with circuit design, verification, and physical design teams in a multicultural environment.
• Ability to manage multiple layout tasks, adhere to project schedules, and maintain high attention to detail and quality under tight deadlines.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field, or equivalent practical experience in IC layout