Physical Design Engineer:
Exp: 8+Yrs
Location: Malaysia
Employment Type: Full-Time
Notice Period: Immediate to 30 Days Preferred.
Role Overview
We are seeking an experienced Physical Design Engineer with 8+ years of ASIC/SoC implementation experience and proven expertise in timing closure across advanced technology nodes. The candidate will be responsible for driving physical design activities from floorplanning through signoff while ensuring PPA (Performance, Power, Area) targets are achieved.
Key Responsibilities
- Perform end-to-end physical design implementation including Floorplanning, Placement, CTS, Routing, and Physical Verification.
- Drive timing closure for block-level and full-chip designs.
- Analyze and resolve setup/hold timing violations.
- Perform ECO implementation and timing optimization.
- Handle congestion, power, area, and performance optimization.
- Execute STA analysis and support signoff activities.
- Collaborate with RTL, STA, DFT, and Verification teams for design convergence.
- Work on IR drop, EM analysis, and physical signoff checks.
- Support tapeout activities and post-layout verification.
Required Skills
- 8+ years of ASIC Physical Design experience.
- Strong expertise in timing closure and STA concepts.
- Hands-on experience with:
- Floorplanning
- Placement & Optimization
- Clock Tree Synthesis (CTS)
- Routing & Physical Verification
- ECO Implementation
- Signoff Timing Closure
- Experience with industry-standard EDA tools such as:
- Synopsys ICC2 / Fusion Compiler
- PrimeTime
- Cadence Innovus
- Tempus
- Good understanding of advanced nodes (16nm/7nm/5nm preferred).
- Knowledge of low-power design techniques and UPF is a plus.
Qualification
- BE/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field.
Mail resumes to *************