全职 Semiconductor Design Verification Engineer 工作, 薪水, Realtek Semiconductor Corp. 公司招聘中 - Ricebowl

Location: Singapore

JOB DESCRIPTION

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition.

• Develop detailed module level and SoC level test plans for all the functional features, based on the design spec.
• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.
• Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working.
• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.
• Collaborate with digital design team to debug functional testcases and deliver functionally correct designs.

The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.

JOB REQUIREMENTS

• Bachelor/Masters in Electronics/Electrical Engineering.
• Level of Expertise: At least 6+ year of SOC/IP verification skills.
• Strong communication, analytical and documentation skills and ability to interface with other groups.
• Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products.
• Strong hardware functional verification language and Object-oriental language development skill.
• Preferred with strong knowledge in System Verilog, UVM, Python (TCL/Perl a plus)
• Familiar with ASIC verification methodology, tools, and development flow.
• Prior experience related to Automotive SoCs, Ethernet/Switch based IPs, High Speed IOs , Memory controllers (like DDR,PSRAM,Flash etc), Video (MIPI/CSI/DSI/HDMI/DP etc) or similar is an added plus.
• Able to handle tasks independent, estimate efforts and deliver results on time.
• Actively participate in resolving issues related to verification tasks in the project.
• Contribute to the overall improvement of verification at IP and SoC levels.