全职 Senior Engineer 工作, 薪水, LanceSoft, Inc. Pulau Pinang 公司招聘中 - Ricebowl

We’re Hiring: Senior Engineer – Semiconductor / ASIC

Location: Penang, Malaysia

Contract: 1 Year (Extendable)

Experience: 5+ Years

Work Type: Onsite

We are looking for an experienced Senior Engineer with strong expertise in ASIC/SoC implementation, Synthesis, STA, LEC, DFT, and timing constraints to join our engineering team in Penang.

Key Responsibilities

• Perform Synthesis, LEC, Low-Power Checks, Memory BIST insertion, and Constraints Validation.

• Collaborate with RTL Design, Physical Design, and DFT teams to identify and resolve synthesis, timing, and constraint-related issues early.

• Run and analyze RTL Lint, CLP, BIST, DFT insertion, and related implementation flows.

• Perform Full-Chip, Subsystem, and Block-Level STA.

• Develop and maintain TCL scripts for design implementation, analysis, and debugging.

• Work hands-on with industry-standard EDA tools including Design Compiler (DC), Genus, Fusion Compiler, PrimeTime, Tempus, Formality, and Conformal.

• Handle ECOs and Logic Equivalence Checking (LEC).

• Mentor and train team members on early-stage implementation flows, tools, and best practices.

• Work independently with Design, DFT, and Physical Design teams to ensure successful netlist delivery and timing constraint validation.

Required Qualifications

• Bachelor’s or Master’s degree in Engineering.

• 5+ years of relevant semiconductor/ASIC/SoC experience.

• Strong understanding of Synthesis methodologies and industry-standard EDA tools.

• Hands-on experience writing timing constraints for Synthesis, STA, and Physical Design.

• Experience performing Full-Chip and Block-Level STA using PrimeTime or Tempus.

• Strong scripting skills in TCL, Perl, and/or Python.

• Ability to work independently with Design, DFT, and Physical Design teams.

• Hands-on experience with ECOs and Logic Equivalence Checking (LEC).

Preferred Qualifications

• Familiarity with DFT methodologies.

• Knowledge of power estimation using vectors and UPF (Unified Power Format).

• Familiarity with additional EDA tools and implementation flows.

• Experience with RTL Development or Physical Design is an added advantage.

Interested, Apply directly through your updated resume.