Role: SoC Design / Synthesis Engineer
Location: Penang, Malaysia
Duration: Long-term Contract
Key Requirements:
- 5+ years of experience in SoC/RTL design or implementation
- Strong experience in RTL coding, Synthesis and RTL Lint
- Hands-on with Design Compiler / Genus / Fusion Compiler
- Experience with STA – PrimeTime/Tempus and timing constraints
- Experience with LEC/Formality/Conformal
- Knowledge of DFT, MBIST, UPF/Low Power
- Strong TCL/Python/Perl scripting skills
- Experience debugging synthesis, timing and equivalence issues
- Good collaboration with RTL, DFT and Physical Design teams
Please let me know if you’re interested, and I can share the complete details and discuss the opportunity further.