Provides DDR technical leadership in the development of new test & validation
Develop and execute system level memory sub-system validation test plans across products.
Closely interacts with silicon design and cross-site memory teams in test execution & debug.
Work closely with validation leader, design, firmware, and software, automation teams to ensure seamless integration and validation
Deliver professional project reports to management, highlight risk in time with solution plans.
Smart and initiative on data analysis to consistently optimize process, efficiency, and quality improvement.
Identify opportunities to improve validation processes, automation tools, and methodologies to enhance efficiency and effectiveness.
Preferred Experience
Demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR/GDDR Memory test experience on electronic components such as Processors would be considered a big plus.
Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR.
Familiar with signal measurement, reading schematics and layout documentation
Requires good written and oral communication skills.
Familiar with Python, Ruby, Perl language.
Self-Motivated with program management skillset.
Academic Credentials
Requires BE+ or master’s degree with 5+ years’ experience.