ADVINNO TECHNOLOGIES PTE. LTD. Hiring! Full Time Senior Photonics Layout Engineer in Central Region (Singapore), Earn up to SGD 5,000 - Ricebowl

Photonics Layout Engineer – Job Description

Job Title

Senior Photonics Layout Engineer

Job Summary

The Photonics Layout Engineer is responsible for the physical layout design, verification, and tape-out of Photonic Integrated Circuits (PICs). The role involves translating photonic circuit schematics into manufacturable layouts while ensuring compliance with foundry design rules, optical performance, and fabrication requirements. The engineer works closely with photonic designers, process engineers, and packaging teams to deliver high-quality silicon photonics and other PIC solutions.

Key Responsibilities

• Develop and maintain physical layouts for Photonic Integrated Circuits (PICs) using industry-standard EDA tools.
• Create layouts for optical components including:WaveguidesGrating couplersRing resonatorsMach-Zehnder Interferometers (MZI)Splitters and combinersPhotodetectorsOptical modulators
• Perform Design Rule Checking (DRC), Layout Versus Schematic (LVS), and layout verification.
• Optimize layouts for optical performance, fabrication yield, and manufacturability.
• Generate GDSII/OASIS files for tape-out.
• Support PDK integration and foundry-specific layout requirements.
• Develop parameterized cells (PCells) and reusable layout libraries.
• Collaborate with photonic circuit designers to implement layout modifications based on simulation results.
• Work with packaging engineers on fiber coupling, alignment marks, and optical I/O structures.
• Assist with wafer fabrication support, silicon validation, and failure analysis.
• Automate layout generation and verification using scripting languages such as Python, Tcl, or SKILL.
• Maintain layout documentation, revision control, and design databases.
• Able to create p cells based on PDK requirement

Required Qualifications

• Bachelor's or Master's degree in:PhotonicsElectrical EngineeringPhysicsMicroelectronicsSemiconductor Engineering
• 2–8+ years of experience in photonic IC layout or semiconductor layout design.
• Understanding of silicon photonics fabrication processes.
• Knowledge of CMOS manufacturing and semiconductor process technologies.

Required Technical Skills

• PIC layout tools (e.g., KLayout, Cadence Virtuoso, Luceda IPKISS, Siemens EDA tools)
• GDSII and OASIS layout formats
• Foundry PDK usage
• DRC/LVS verification
• Waveguide routing and optical component layout
• Mask layout preparation and tape-out flow
• Python, Tcl, or SKILL scripting
• Version control systems (Git or SVN